The majority of digital electronic circuits in use today are integrated circuits of varying complexity, fabricated in the semiconductor material silicon. Digital circuits are subdivided into logic families corresponding to the interface protocols to which they adhere. The most common of these logic families are TTL (transistor-transistor logic) and ECL (Emitter-coupled logic), which include specifications of power supply forms and input and output signal levels for interfacing with circuits in the same logic family.
In addition to the predominant technology which is based on silicon, other technologies are available for implementing digital integrated circuits. Among these is the compound semiconductor logic based on gallium arsenide (GaAs). GaAs logic is faster than silicon logic and can be used for this reason within silicon logic circuits to achieve great advantages. However, silicon and GaAs logic circuits are characterized by different threshold voltages, which define the interface protocols between logical high states (digital value one) and logical low states (digital value zero). Thus, any composite digital logic system must include input and output buffer circuitry to shift voltage levels between the silicon logic circuits and the GaAs logic circuits, while preserving the corresponding digital value.
FIG. 1 is a block diagram of a typical system for interfacing silicon and compound semiconductor digital logic circuits. A silicon integrated circuit 10 is connected to input buffers 16, which are in turn connected to a compound semiconductor integrated circuit 14. The input buffers 16 transform signals within the silicon logic protocols of the silicon integrated circuit 10 to corresponding input signal levels within the logic protocols of the semiconductor technology of the integrated circuit 14. Output buffers 18, which are connected between the integrated circuit 14 and a silicon integrated circuit 12, then transform the output signals generated by the integrated circuit 14 into corresponding signal levels within the logic protocols of silicon.
FIGS. 2, 3 and 4 depict typical circuits for GaAs input buffers, which are based on MESFETs. These circuits can be classified roughly into two different categories, depending on whether or not a source follower input is used. Each of the depicted circuits exhibit numerous disadvantages, which are discussed below.
The circuits of FIGS. 2 and 3 show examples of the input buffer circuits disclosed in U.S. Pat. No. 4,791,322 to Graham et al., which are based on source follower designs. Depletion mode MESFETs 20, 20a are connected as source followers with their gates serving as buffer inputs 22, 22a and their drains connected to a positive voltage supply V.sub.cc. In FIG. 2, the source of the MESFET 20 has a conduction path to the negative voltage supply V.sub.ss through a diode chain 24 and to a second depletion mode MESFET 26 which is biased into conduction. Similarly, in FIG. 3, the source of MESFET 20a is connected to a negative voltage supply through a diode chain 24a and resistors 28a, 29a.
The input buffer circuits of FIGS. 2 and 3 require positive and negative voltage supplies Standard semiconductor logic, on the other hand, is based on a single positive supply. As a result, negative voltage supplies must be externally added to any system using these input buffer circuits.
The circuits of FIGS. 2 and 3 rely on the diode chains 24 and 24a, respectively, to shift the voltage level from the driving digital logic circuit to the voltage level corresponding to the same digital value in the protocol of the driven digital logic circuit. Since the actual voltage drop depends on the drop across the individual devices, the shifted voltage level will be sensitive to process and temperature variations in the individual devices. The shifted voltages of the circuits of FIGS. 2 and 3 are also sensitive to the power supply voltages The input signal threshold voltage of the circuit in FIG. 3 is especially dependent on V.sub.ss. Consequently, the input to the driven digital logic circuit may not switch between low and high states when the output of the digital logic driving the circuit does so.
Finally, the circuit of FIG. 2 is poorly designed to cope with input voltages above V.sub.cc. When input voltages exceed V.sub.cc, the gate-to-drain diode of the MESFET 20 clamps the input at one diode drop above V.sub.cc, i.e. approximately 5.8 volts. However, with the MESFETs 20 and 26 conducting, the path to ground via these MESFETs and the diode chain 24 corresponds to approximately 4 volts, resulting in instabilities in the input. In addition, high input voltages require that the input MESFET 20 be capable of conducting large currents, which increase the likelihood of damage to the device.
FIG. 4 shows an another typical input buffer circuit, which is disclosed in U.S. Pat. No. 4,791,322 to Graham et al. The circuit of FIG. 4 eliminates the additional negative power supplies of the circuits shown in FIGS. 2 and 3, but it also eliminates the high input impedance provided by the source follower input, creating problems of its own. The input 30 is connected to the gate of an enhancement mode MESFET 40 by means of a diode 32, which is reverse biased in the direction of the input signal to the buffer circuit, and two enhancement mode MESFETS 34, 36 connected in series A depletion mode MESFET 38 has its drain connected to the positive voltage supply, V.sub.cc, and its source connected to its gate and to the gate of the enhancement mode MESFET 40 through a resistor 42.
When the input 30 is taken high by the driving source, the diode 32 prevents any large current flows into the buffer circuit. However, when the input 30 swings low, the circuit sources current into the driving circuit from V.sub.cc via the MESFETs 34, 36, 38, the resistor 42 and the diode 32. The current sinking requirement imposed on the driving circuit by this circuit limits the capability of the driving circuit to drive multiple devices (i.e., limits the fanout of the driving circuit).
The voltage level shift from driving source logic levels to those of the buffer and internal circuitry is achieved by means of two level shifting elements. The first level shifting element is the depletion mode MESFET 38, which sources current across the MESFETs 34 and 36 and is operative for low voltage inputs. The second level shifting element, operative for high inputs, is provided by the drain current through a MESFET 44, which ensures a voltage drop across diodes 46, 48. As with the circuits of FIGS. 2 and 3, discussed above, the dependence of the circuit of FIG. 4 on the MESFET 44 and the diodes 46, 48 for the necessary level shifts makes the output voltage sensitive to process variations in the devices and to operating temperatures of the circuit. In addition, variations in the supply voltage will also effect the output voltage. Also, the circuit of FIG. 4 provides no simple way to adjust the output voltage level for different types of silicon or compound semiconductor logic.
Typical output buffers known in the art present a different set of disadvantages with regard to smooth integration between silicon and compound digital logic. For example, certain typical output buffer circuits require both positive and negative voltage supplies. As discussed above, the negative supply is not standard to silicon based logic and must be supplied externally for these circuits. Additionally, while the advantages of three state functionality are well known in the art, it has not been regularly used in output buffer circuits designed for GaAs for the reasons discussed below.
Three state functionality refers to the capability of putting a circuit's output in a high impedance state in addition to the normal high and low logic states. In this tri-state, the output is disconnected from both the power supply and ground. FIG. 5 shows a typical active high three state buffer 50. This buffer is either enabled to pass a signal from its input 52 to its output 54 or to assert the tri-state at its output 54, depending on whether its enable/disable terminal 56 is high or low.
A barrier to the implementation of tri-state functionality in GaAs technology arises from the relatively low threshold voltage of GaAs enhancement mode devices. Typically, V.sub.th is 0.2 volts. However, worst case process variations may reduce this to 0.15 volts and the temperature dependence of the device may further reduce V.sub.th to as little as 75 millivolts. Thus, in order to fully turn off a MESFET with its source connected to ground, the gate must be pulled reliably below 75 millivolts. A logic input that is not sufficiently low to turn an output MESFET off hard results in sub-threshold leakage current in the channel of the pull-down MESFET, which reduces the output impedance of the circuit in the tri-state.
FIG. 6 illustrates a typical three state output buffer circuit for interfacing compound semiconductor digital logic circuits with silicon digital logic circuits, which is disclosed in U.S. Pat. No. 4,884,563 to MacMillan et al. The output buffer of FIG. 6 incorporates a tri-state input stage 70, three buffer stages 72, 74 and 76, and a standard totem pole output configuration 78. The output configuration 78 is based on MESFETs 80, 82 which pull an output 84 to the corresponding supply rail when turned on.
The output of the tri-state input stage 71 inverts the input level and applies it to the gates of four enhancement mode MESFETs 86, 88, 90, 92. These MESFETS have their sources connected to ground and their drains connected to the drains of MESFETs 98, 100, 102, 104, respectively, on the outputs of the stages 72, 74. Thus, a high voltage level to the tri-state input stage 71, is inverted to low, shutting off the MESFETs 86, 88, 90, 92 and allowing an input 73 of the buffer stage 72 to be passed to the output terminal 84. A low voltage level to the tri-state input stage 71 is inverted by that stage to a high logic state, which is applied to the gates of the MESFETs 86, 88, 90, 92, turning them on. As a result, point A, which is connected to the gate of the MESFET 80, is pulled low, shutting off the pull-up MESFET 80 and isolating the output 84 from the high voltage rail. Similarly, point B is pulled low, shutting off the pull-down MESFET 82.
Since the source of MESFET 82 is at ground, its gate must be pulled below ground to ensure that the MESFET 80 is shut off hard. The circuit of FIG. 6 ensures hard shut off by connecting an on-chip negative charge pump to the source of the depletion mode MESFET 96 via a resistor 97. With the depletion mode MESFET 96 biased into conduction, the negative charge pump ensures that the gate of the MESFET 82 is pulled below ground.
This use of the on-chip negative charge pump to ensure hard shut off of the pull-down MESFET 82 is a severely limited solution to the sub-threshold leakage problem. The charge pump occupies space on the chip and can only provide negative voltage to a limited number of driven outputs, since the current needed from the charge pump for a large number of outputs makes the charge pump circuit prohibitive.